1. Field of the Invention
The present invention generally relates to circuits implemented with interconnect wiring switches and, more particularly, a switching function is implemented using a metal-oxide switch that is reprogrammable.
2. Description of the Related Art
A Field Programmable Gate Array (FPGA) is a type of integrated circuit that can be reconfigured using electrically programmable switches in order to realize a large range of arbitrary functions. FIG. 1 exemplarily shows a conventional FPGA architecture 100 that includes an array of tiles, and each tile 10 includes two connection blocks (CB) 20, one logic block (LB) 30 and one switch block (SB) 40. Each LB 30 generally includes a cluster of basic logic elements (BLEs), typically lookup tables (LUTs) and circuits required to use these, to provide customizable logic functions.
Wire segments 50, which are wires that are unbroken by a programmable switch, are connected with each other through SBs 40. A sequence of one or more wire segments 50 in a line is referred to herein as a track and a group of parallel tracks is referred to herein as a routing channel 60. The LBs 30 are connected to routing channels 60 through CBs 20.
The CB 20 performs input/output between the LB 30 and wire segments 50 and the SB 40 switches connections of the wire segments 50. The switching of the wire segments 50 in the SB 40 or the input/output in the CB 20 is controlled by using electrically programmable switches. It is noted that, in the configuration exemplarily denoted in FIG. 1, LBs 30 and CBs 20 are also used to interconnect each tile unit 10 to its adjacent tile units.
In arriving at the concepts described herein, the present inventors realized that there is a problem in the conventional FPGAs, in that these CBs 20 and SBs 40 account for a large majority of a conventional FPGA's total area, delay, and power consumption.
More specifically, as is shown in FIG. 1, a typical circuit design of the CBs 20 uses Static Random Access Memory (SRAM) cells 70 to control pass gate transistors 80. It should be noted that the SRAM cells can also be used to control the selector pin of a multiplexer (MUX) as well. The pass gate transistor 80 acts as either a closed switch or an open switch according to a value of a bit of the SRAM cell 70.
Each of the SRAM cells 70 is generally a six-transistor (6T) cell that includes two inverters each including an N-type transistor and a P-type transistor, and two N-type transistors connected to a row line. The output of each of the SRAM cells 70 is generally connected to a pass gate transistor 80 (or the selector pin of a MUX). The pass gate transistor 80 is relatively larger than the transistors of the SRAM cell 70.
In the conventional technology FPGA architecture, these circuit components are formed in the Si wafer substrate. Also in the conventional technology FPGA architecture, information stored in the SRAM cells is volatile, meaning it is lost when the circuit is powered down.
Additionally, the present inventors have recognized that other types of circuits that rely on a switching function also have problems. For example, another conventional technology provides a smaller sized programmable switch called an “antifuse”. An antifuse is a device that has two terminals and presents an open circuit when unprogrammed. To program the antifuse, e.g., cause it to present a closed circuit, a current pulse is applied across the terminals causing the antifuse to blow and create a permanent connection between two wires.
However, antifuses are only able to be programmed once and, thereafter, are no longer re-programmable. As a result, they are not suitable for applications which may require multiple instances of reprogramming. This is also true for the eFuse device. Generally, antifuse and eFuse devices are used to select from redundant memory arrays at the time of chip testing to increase the chip yield.
Accordingly, the present inventors have recognized that there exists a need to improve such circuits as FPGAs and microprocessors that utilize redundant cache memory arrays or redundant circuit blocks.
Similarly, a need is recognized to exist for a way to engage in performance tuning of a chip such that the function of the chip (or a sub-system thereof) relative to a certain reprogrammable switch can be reprogrammed multiple times, as well as other circuit types that would benefit from a reduction of area devoted to the switching function, particularly if reprogrammability is also a desirable feature for the switching function.
In addition, there is a need to retain any reprogrammed information in a non-volatile device when the circuit is powered down, thus enabling rapid return to the same state when the chip is turned on.